1. Field of the Invention
The present invention relates to a plastic-molded-type semiconductor device and a producing method therefor, and in particular, to a plastic-molded-type semiconductor device suitable to attain a higher level of device integration and a producing method therefor.
2. Description of the Prior Art
Encasing a plurality of semiconductor chips in a single packaged unit is directly effective in attaining a higher level of device integration.
It may not be so effective in attaining a higher level of device integration to arrange a plurality of semiconductor chips in a plane, because the outer size of the package becomes rather large. Therefore, it is required to pile a plurality of semiconductor chips one upon another in a package in order to achieve a high integration of the device.
There are disclosed several methods of piling a plurality of semiconductor chips one upon another in a package. One of the methods is to mount semiconductor chips on each side of a chips pad, as disclosed, for example, in Japanese Patent Application Laid-open No. 62-8529, No. 62-131555, No. 1-220837, or No. 1-257361.
A method of piling two semiconductor chips having different sizes one upon another is disclosed in Japanese Patent Application Laid-open No. 1-295454 or No. 2-15660.
Further, a structure, in which each of a plurality of semiconductor chips is mounted on each of a plurality of lead frames each composed of an outer lead and an inner lead, respectively, and these semiconductor chips are piled one upon another, as forming many layers, so as to seal them, is disclosed in Japanese Patent Application Laid-open No. 63-124450 or No. 63-220559.
Another method of piling a plurality of semiconductor chips and mounting them in one package unit, in which semiconductor chips are connected with lead frames using a special method, is disclosed in Japanese Patent Application Laid-open No. 61-59862 or No. 1-99248. Further another method, in which piled lead frames in many layers are electrically connected inside of the package to each other, is disclosed in Japanese Patent Application Laid-open No. 62-119952.
Further, Japanese Patent Application Laid-open No. 62-260352 or No. 62-293749 discloses a method of mounting a plurality of semiconductor chips on a substrate with each of the semiconductor chips arranged perpendicular to the substrate.
Among the above-mentioned methods of prior arts, the method of mounting semiconductor chips on both sides of a chip pad can not provide a high level integration more than two chips, because the number of semiconductor chips is essentially only two chips. In addition, it is difficult in this method to electrically connect the chips mounted on the both sides of the chip pad with the lead frames through electric wires.
The method of piling a plurality of chips having various sizes one upon another and mounting them thereon can not be adopted when a plurality of semiconductor chips each having the same size such as memory chips, for example, are to be mounted for achieving a high level integration. Further, when the height differences between the semiconductor chips and the lead frames are greater, there is caused a disadvantage that the wires are apt to contact with the corners of the semiconductor chips.
The method performed using a plurality of lead frames makes impossible a plastic-molding method utilizing a transfer-molding method, which is widely used at the present time, because several layers of outer leads project on the package surface form. Therefore, this method is unsuitable to a mass-production.
The method performed using a special method of electrically connecting the chips with the lead frames is difficult to be brought in practice, because the reliability of connection according to this method is judged insufficient when compared with the conventional connection through wires on the base of the data as far as disclosed in the known references.
The method of arranging semiconductor chips perpendicular to the chip pad adopts a special method for electrically connecting the chips with the substrate, and therefore, as mentioned above, is difficult to be brought in practice. These methods require to arrange the electrodes of the chips unevenly near one side of the device, thereby causing a disadvantage that the degree of design freedom for chips is decreased.
In the method of connecting a plurality of lead frames piled up in several layers with one another inside of the package unit, since the inside leads connected with the outside leads are arranged in parallel to the chips, the number of the semiconductor chips to be encased in a package unit is limited below three chips in the structure.
Further, the above known methods include a common disadvantage that no consideration is paid to the discharge of the heat, which is generated in a great amount when the number of chips increases, towards the outside of the package unit.